Sains Malaysiana 46(7)(2017): 1089–1095

http://dx.doi.org/10.17576/jsm-2017-4607-11

 

Performance Characterization of Schottky Tunneling Graphene Field Effect Transistor

at 60 nm Gate Length

(Pencirian Prestasi Saluran Schottky Grafin Transistor pada Panjang Get 60 nm)

 

NOOR FAIZAH ZAINUL ABIDIN¹, IBRAHIM AHMAD¹*, PIN JERN KER¹ & P. SUSTHITHA MENON²

 

¹Centre for Micro and Nano Engineering (CeMNE), College of Engineering, Universiti Tenaga Nasional (UNITEN), 43009 Kajang, Selangor Darul Ehsan, Malaysia

 

²Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 UKM Bangi, Selangor Darul Ehsan, Malaysia

 

Received: 26 December 2016/Accepted: 1 March 2017

 

ABSTRACT

A planar Graphene Field-Effect Transistor GFET performance with 60 nm gate length was evaluated in discovering new material to meet the relentless demand for higher performance-power saving features. The ATHENA and ATLAS modules of SILVACO TCAD simulation tool was employed to virtually design and assess the electrical performance of GFET. The developed model was benchmarked with the established results obtained from the DESSIS simulator model by using the same graphene channel’s parameters and simulated at fixed threshold voltage of 0.4V. The GFET was also analyzed and ranked its performance for four different gate oxides which includes HfO₂, Al₂O₃, TiO₂, and Ta₂O₅. Compared to the benchmarked device, our GFET shows a competitive performance although it possesses a lower drive current (ION). However, the leakage current (IOFF), subthreshold swing (SS) and the device’s switching capability (ION/IOFF) are more superior than those of the benchmarked device, with an improvement of 99%, 48.3% and 99.36%, respectively. The with different gate dielectrics were also proven to possess a lower IOFF, competitive ION, smaller SS and better switching capability compared to the established DESSISS model. The graphene parameters in this experiment can be utilized for further optimization of GFET with smaller gate lengths.

 

Keywords: Graphene; high-k dielectric; SILVACO

 

ABSTRAK

Prestasi satah panjang pintu 60 nm Grafin transistor GFET dinilai dalam pelapisan bahan baru untuk memenuhi permintaan yang tidak henti-henti untuk ciri-ciri penjimatan prestasi kuasa yang lebih tinggi. GFET yang dianalisis menggunakan ATHENA dan ATLAS modul dalam perisisan Silvaco TCAD mereka bentuk transistor dan menilai prestasi elektrik. Model yang dibangunkan ditanda aras dengan keputusan mantap daripada perisian DESSIS model dengan menggunakan parameter saluran grafin yang sama dan simulasi pada voltan ambang tetap 0.4V. Prestasi GFET juga dianalisis di empat oksida pintu yang berbeza yang termasuklah HfO₂, Al₂O₃, TiO₂ dan Ta₂O₅. Keputusan peranti menunjukkan prestasi peranti yang berdaya saing dengan peranti asas dan parameter struktur walaupun ia mempunyai arus semasa yang lebih rendah (ION). Kebocoran arus (IOFF), sub ambang swing (SS) dan keupayaan pensuisan peranti (ION/IOFF) bagaimanapun telah menunjukkan ciri peranti besar dengan peningkatan masing-masing sebanyak 99%, 48.3% dan 99.36%. Keputusan menggunakan dielektrik pintu yang berbeza juga menghasilkan IOFF yang lebih rendah, ION yang berdaya saing,, SS yang lebih kecil dan keupayaan pensuisan yang lebih baik berbanding model DESSISS yang ditubuhkan yang mana parameter grafin dalam eksperimen ini boleh digunakan untuk pengoptimuman dan mereka bentuk peranti dengan panjang pintu yang lebih kecil.

 

Kata kunci: Dielektrik tinggi-k; grafin; SILVACO

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*Corresponding author; email: AIbrahim@uniten.edu.my